? semiconductor components industries, llc, 2014 april, 2014 ? rev. 0 1 publication order number: ntlus3c18pz/d ntlus3c18pz power mosfet ?12 v, ?7.0 a, cool single p?channel, 1.6x1.6x0.5 mm cool udfn6 package features ? ultra low r ds(on) ? udfn package with exposed drain pads for excellent thermal conduction ? low profile udfn 1.6 x 1.6 x 0.5 mm for board space saving ? these devices are pb?free, halogen free/bfr free and are rohs compliant applications ? optimized for power management applications for portable products, such as smart phones and media tablets ? battery switch ? high side load switch maximum ratings (t j = 25 c unless otherwise stated) parameter symbol value unit drain-to-source voltage v dss ?12 v gate-to-source voltage v gs 8 v continuous drain current (note 1) steady state t a = 25 c i d ?7.0 a t a = 85 c ?5.1 t 5 s t a = 25 c ?10.5 power dissipa- tion (note 1) steady state t a = 25 c p d 1.71 w t 5 s t a = 25 c 3.83 continuous drain current (note 2) steady state t a = 25 c i d ?4.4 a t a = 85 c ?3.1 power dissipation (note 2) t a = 25 c p d 0.66 w pulsed drain current tp = 10 s i dm ?21 a operating junction and storage temperature t j , t stg -55 to 150 c source current (body diode) (note 2) i s ?1.7 a lead temperature for soldering purposes (1/8 from case for 10 s) t l 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. surface mounted on fr4 board using 1 in sq pad size (cu area = 1.127 in sq [2 oz] including traces). 2. surface-mounted on fr4 board using the minimum recommended pad size of 30 mm 2 , 2 oz. cu. http://onsemi.com p?channel mosfet ?12 v 27 m @ ?3.7 v 24 m @ ?4.5 v r ds(on) max i d max v (br)dss mosfet udfn6 ( cool ) case 517au see detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. ordering information aa = specific device code m = date code = pb?free package 30 m @ ?3.3 v marking diagram (top view) (*note: microdot may be in either location) ?7.0 a s d g pin connections ?6.6 a ?6.3 a aam 1 1 6 36 m @ ?2.5 v 70 m @ ?1.8 v ?5.7 a ?4.1 a
ntlus3c18pz http://onsemi.com 2 thermal resistance ratings parameter symbol max unit junction-to-ambient ? steady state (note 3) r ja 72 c/w junction-to-ambient ? t 5 s (note 3) r ja 32.6 junction-to-ambient ? steady state min pad (note 4) r ja 190.4 3. surface-mounted on fr4 board using 1 in sq pad size (cu area = 1.127 in sq [2 oz] including traces). 4. surface-mounted on fr4 board using the minimum recommended pad size of 30 mm 2 , 2 oz. cu. electrical characteristics (t j = 25 c unless otherwise specified) parameter symbol test condition min typ max units off characteristics drain-to-source breakdown voltage v (br)dss v gs = 0 v, i d = ?250 a ?12 v drain-to-source breakdown voltage temperature coefficient v (br)dss /t j i d = ?250 a, ref to 25 c 7.3 mv/ c zero gate voltage drain current i dss v gs = 0 v, v ds = ?9.6 v t j = 25 c ?1.0 a gate-to-source leakage current i gss v ds = 0 v, v gs = 8 v 10 a on characteristics (note 5) gate threshold voltage v gs(th) v gs = v ds , i d = ?250 a ?0.4 ?1.0 v negative threshold temp. coefficient v gs(th) /t j 3.0 mv/ c drain-to-source on resistance r ds(on) v gs = ?4.5 v, i d = ?7.0 a 20 24 m v gs = ?3.7 v, i d = ?6.6 a 22 27 v gs = ?3.3 v, i d = ?5.7 a 24 30 v gs = ?2.5 v, i d = ?5.1 a 29 36 v gs = ?1.8 v, i d = ?2.0 a 44 70 forward transconductance g fs v ds = ?5 v, i d = ?7.0 a 21.8 s charges, capacitances & gate resistance input capacitance c iss v gs = 0 v, f = 1 mhz, v ds = ?6.0 v 1570 pf output capacitance c oss 200 reverse transfer capacitance c rss 240 total gate charge q g(tot) v gs = ?4.5 v, v ds = ?6.0 v; i d = ?7.0 a 15.8 nc threshold gate charge q g(th) 0.7 gate-to-source charge q gs 1.9 gate-to-drain charge q gd 4.6 switching characteristics (note 6) turn-on delay time t d(on) v gs = ?4.5 v, v dd = ?6 v, i d = ?7.0 a, r g = 1 8.5 ns rise time t r 52.5 turn-off delay time t d(off) 40 fall time t f 59 drain-source diode characteristics forward diode voltage v sd v gs = 0 v, i s = ?1.7 a t j = 25 c 0.71 1.0 v t j = 125 c 0.58 5. pulse test: pulse width 300 s, duty cycle 2%. 6. switching characteristics are independent of operating junction temperatures. product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions.
ntlus3c18pz http://onsemi.com 3 typical characteristics figure 1. on?region characteristics figure 2. transfer characteristics ?v ds , drain?to?source voltage (v) ?v gs , gate?t o?source voltage (v) 2.0 1.5 1.0 0.5 0 0 5 10 15 2.5 2.0 1.5 1.0 0.5 0 0 5 10 15 figure 3. on?resistance vs. gate?to?source voltage figure 4. on?resistance vs. drain current and gate voltage ?v gs , gate voltage (v) ?i d , drain current (a) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 20 15 10 5 0 0 0.01 0.02 0.03 0.04 0.05 figure 5. on?resistance variation with temperature figure 6. drain?to?source leakage current vs. voltage t j , junction temperature ( c) ?v ds , drain?to?source voltage (v) 125 100 75 50 25 0 ?25 ?50 0.7 0.8 0.9 1.1 1.2 1.3 1.4 1.6 12 10 8 6 4 2 1e?09 1e?08 1e?07 1e?06 1e?05 ?i d , drain current (a) ?i d , drain current (a) r ds(on) , drain?to?source resistance ( ) r ds(on) , normalized drain?to? source resistance ( ) ?i dss , leakage (na) . v gs = ?1.8 v v gs = ?2.0 v ?4.5 v to ?2.5 v v ds ?10 v t j = 125 c t j = 25 c t j = ?55 c t j = 25 c i d = ?7 a r ds(on) , drain?to?source resistance ( ) t j = 25 c v gs = ?1.8 v v gs = ?2.5 v v gs = ?4.5 v 150 1.0 1.5 v gs = ?4.5 v i d = ?7 a t j = 125 c t j = 85 c
ntlus3c18pz http://onsemi.com 4 typical characteristics figure 7. capacitance variation figure 8. gate?to?source and drain?to?source voltage vs. total charge ?v ds , drain?to?source (v) q g , total gate charge (nc) 12 10 8 6 4 2 0 0 500 1000 1500 2000 2500 16 14 12 8 6 4 2 0 0 1 2 3 4 5 figure 9. resistive switching time variation vs. gate resistance figure 10. diode forward voltage vs. current r g , gate resistance ( ) ?v sd , source?to?drain voltage (v) 100 10 1 1 10 100 1000 0.9 0.8 1.0 0.7 0.6 0.5 0.4 0.3 0.1 1 10 figure 11. threshold voltage figure 12. maximum rated forward biased safe operating area t j , junction temperature ( c) ?v ds , drain?to?source voltage (v) 125 100 75 50 25 0 ?25 ?50 0.15 0.25 0.35 0.45 0.55 0.75 0.85 0.95 100 10 1 0.1 0.01 0.1 1 10 100 c, capacitance (pf) ?v gs , gate?t o?source voltage (v) t, time (ns) ?i s , source current (a) ?v gs(th) (v) ?i d , drain current (a) c iss c oss c rss v gs = 0 v t j = 25 c f = 1 mhz 10 18 ?v ds , drain?to?source voltage (v) 0 4 8 12 16 18 14 10 6 2 v ds = ?6 v t j = 25 c i d = ?10 a q t q gs v gs q gd v gs = ?4.5 v v dd = ?6 v i d = ?10 a t f t r t d(off) t d(on) t j = 125 c t j = 25 c t j = ?55 c i d = ?250 a 150 0.65 v gs = ?8 v single pulse t c = 25 c 10 s 100 s 1 ms 10 ms dc r ds(on) limit thermal limit package limit
ntlus3c18pz http://onsemi.com 5 typical characteristics t, time (s) 1e+00 1e?03 1e+01 1e?04 1e?02 1e?05 1e?01 1e?06 0 10 20 30 50 60 70 80 r(t), effective transient thermal response 40 1e+02 1e+03 duty cycle = 0.5 single pulse 0.20 0.10 0.05 0.02 0.01 r ja = 72 c/w figure 13. single pulse maximum power dissipation single pulse time (s) 1e+03 1e+01 1e?01 1e?03 1e?05 0 25 75 100 125 150 175 225 power (w) figure 14. fet thermal response 50 200 device ordering information device package shipping ? ntlus3c18pztag udfn6 (pb?free) 3000 / tape & reel NTLUS3C18PZTBG udfn6 (pb?free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ntlus3c18pz http://onsemi.com 6 package dimensions udfn6 1.6x1.6, 0.5p case 517au issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. a b e d d2 e2 bottom view b e 6x 0.10 b 0.05 a c c note 3 2x 0.10 c pin one reference top view 2x 0.10 c note 4 a a1 (a3) 0.05 c 0.05 c c seating plane side view l 6x 1 3 4 6 dim min max millimeters a 0.45 0.55 a1 0.00 0.05 a3 0.13 ref b 0.20 0.30 d 1.60 bsc d2 0.15 0.25 e 1.60 bsc e2 0.57 0.67 e 0.50 bsc l 0.20 0.30 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. mounting footprint* l1 detail a 0.82 0.43 0.50 pitch 0.35 2x 1.90 dimensions: millimeters 0.32 1 6x soldermask defined l1 ??? 0.15 f 0.55 bsc g 0.25 bsc d1 0.62 0.72 d1 g f 0.10 b a c 0.10 b a c 0.16 0.28 0.68 on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ntlus3c18pz/d cool is a trademark of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative
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